Research Projects Directory

PI Akhan Almagambetov

CO-I David Feinauer

CO-I Holly Ross

Bit-serial multipliers have a variety of applications, from the implementation of neural networks to cryptography. The advantage of a bit-serial multiplier is its relatively small footprint, when implemented on a Field Programmable Gate Array (FPGA) device. Despite their apparent advantages, however, traditional bit-serial multipliers typically require a substantial overhead, in terms of component usage, which directly translates to a large area of the chip being reserved while many of those resources are unused.

This research addresses the possibility of an efficient two's complement bit-serial multiplier (serial-serial multiplier) implementation that would minimize flip-flop and control set usage on an FPGA device, thereby potentially reducing the overall area of the circuit. Since the proposed architecture is modular, it functions as a "generic" definition that can be effortlessly implemented on an FPGA device for any number of bits.

PI Sean Jeralds

PI Aaron Clevenger

PI Ronald Madler

CO-I Ashish Amresh

PI Matthew Jaffe

PI Samuel Siewert

CO-I Matthew Vis

CO-I Ryan Claus

CO-I Nicholas DiPinto

This research focuses on the development of field deployed multi-spectral computer vision systems for use on maritime vessels, buoys, ports, and for use on unoccupied aerial systems. The approach includes development of both General Purpose Graphics Processing Unit and multi-core image processing along with Field Programmable Gate Array (FPGA) hybrid architectures for low-power real-time computer vision. The mission is detection and monitoring of security, environmental and safety threats in Arctic maritime environments.

PI Nicholas Devereux

CO-I Paul Hriljac

PI Michael Hickey

PI Archie Dickey

PI Timothy Sestak