1-2 of 2 results
-
Novel n x n Bit-Serial Multiplier Architecture Optimized for Field Programmable Gate Arrays (FPGA)
PI Akhan Almagambetov
CO-I David Feinauer
CO-I Holly Ross
Bit-serial multipliers have a variety of applications, from the implementation of neural networks to cryptography. The advantage of a bit-serial multiplier is its relatively small footprint, when implemented on a Field Programmable Gate Array (FPGA) device. Despite their apparent advantages, however, traditional bit-serial multipliers typically require a substantial overhead, in terms of component usage, which directly translates to a large area of the chip being reserved while many of those resources are unused.
This research addresses the possibility of an efficient two's complement bit-serial multiplier (serial-serial multiplier) implementation that would minimize flip-flop and control set usage on an FPGA device, thereby potentially reducing the overall area of the circuit. Since the proposed architecture is modular, it functions as a "generic" definition that can be effortlessly implemented on an FPGA device for any number of bits.
Categories: Faculty-Staff
-
A Curriculum Wide Software Development Case Study
PI Massood Towhidnejad
CO-I Thomas Hilburn
This NSF funded research develops case studies of software development for use in software engineering and computing instruction.
Products include realistic projects, complete artifacts throughout the software development life cycle, case studies decoupled from a particular textbook, and case modules designed with varying complexity allowing for use in multiple classes throughout undergraduate and graduate curricula.Categories: Faculty-Staff
1-2 of 2 results