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Displaying 1-4 of 4 Results

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A Knowledge-based Consultant for Diagnosing Toxic Exposures

  • PI Joel Schipper

  • Joel Schipper of the Computer, Electrical, and Software Engineering Department works with Toxicologist Kim An Nguyen of Claude Bernard University Lyon 1, developing a knowledge-based system to aid in the timely diagnosis of exposures to unknown toxins.

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ICARUS Drone Net

  • PI Samuel Siewert

    CO-I Iacopo Gentilini

    CO-I Mehran Andalibi

    CO-I Stephen Bruder

  • Drone Net is a conceptual architecture to integrate passive sensor nodes in a local sensor network along with traditional active sensing methods for small Unmanned Aerial Systems traffic management. The goal of the proposed research architecture is to evaluate use of multiple passive sensor nodes integrating Electro-Optical/Infrared and acoustic arrays networked around a UAS Traffic Management operating region (Class G uncontrolled airspace). The Drone Net approach will be compared to and/or used in addition to RADAR and Automatic Dependent Surveillance-Broadcast tracking and identification.  We hypothesize that this approach can better manage non-compliant small UAS along with compliant UAS and general aviation in sensitive airspace, urban locations, and geo-fenced regions. 

Identifying Cost-Effective Security Barrier Technologies for K-12 Schools: An Interdisciplinary Evaluation

  • PI Thomas Foley

    CO-I Reginald Parker

    CO-I Michele Gazica

    CO-I Brooke Shannon

    CO-I Erin Bowen

    CO-I Muna Slewa

    CO-I Michael Brady

    CO-I Richard Rodriguez

    CO-I Perry Feder

  • This study proposes to test and collect data on the effectiveness of commonly used physical security systems in delaying intruders. The purpose of this study is to support the design of better physical security systems for schools. The study will also gather data on parent and teacher perceptions of the quality of security in schools.

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Novel n x n Bit-Serial Multiplier Architecture Optimized for Field Programmable Gate Arrays (FPGA)

  • PI Akhan Almagambetov

    CO-I David Feinauer

    CO-I Holly Ross

  • Bit-serial multipliers have a variety of applications, from the implementation of neural networks to cryptography. The advantage of a bit-serial multiplier is its relatively small footprint, when implemented on a Field Programmable Gate Array (FPGA) device. Despite their apparent advantages, however, traditional bit-serial multipliers typically require a substantial overhead, in terms of component usage, which directly translates to a large area of the chip being reserved while many of those resources are unused.

    This research addresses the possibility of an efficient two's complement bit-serial multiplier (serial-serial multiplier) implementation that would minimize flip-flop and control set usage on an FPGA device, thereby potentially reducing the overall area of the circuit. Since the proposed architecture is modular, it functions as a "generic" definition that can be effortlessly implemented on an FPGA device for any number of bits.